The present invention relates to integrated circuits, in particular universal asynchronous receiver transmitters (UARTs), and more particularly to wake-up sequences.
A UART is typically used in communications to convert a data stream from parallel to serial. This enables a serial data stream to communicate with a central processing unit or CPU. In order to conserve energy, the UART may be put in a sleep mode where its oscillator is put to sleep as well.
Upon a subsequent start-up of the UART, it will take some amount of time before the oscillator is stable and the data transmitted or received can be guaranteed to be stable. Unlike a microprocessor, where it cannot operate until the clock is stable, data could be sent to a UART before knowing whether its clock was stable or not.
The typical approach for dealing with the wake-up of a UART is to set forth in the specification for the UART that a certain period of time must be allowed to pass after the UART is awakened and before data is transmitted or received. If an attempt is made to transmit or receive data too soon, before the clock is stable, the data can be corrupted. The specified waiting time must be sufficiently long to account for variations in the process and stability of the oscillator from wafer to wafer, and also to account for other variations. Accordingly, the specified time is often longer than necessary, imposing an additional delay on the system.
The present invention provides a UART with a clock oscillator that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator is awakened, the counter counts up to a specified count. Upon reaching the specified count, an output of the counter is enabled which is connected to an interrupt line for generating an interrupt.
In one embodiment, the IC need not be a UART, and no interrupt code is provided for the interrupt, thus eliminating the need for an additional interrupt register or additional room in existing interrupt registers. The user, such as a CPU, upon receiving the interrupt will look for an interrupt code. The absence of the interrupt code (or the presence of all zeros or some other default value not associated with another interrupt code), combined with the user""s knowledge that the integrated circuit was previously asleep, allows the user to determine that the interrupt indicates a clock wake-up.
In a preferred embodiment, the integrated circuit is a UART device. The counter can be programmed to a value corresponding to the time to achieve stability for the clock. This could be done on a device-by-device or wafer-by-wafer basis, if desired. Alternately, a single conservative value could be used for the counter. Eight bits has been chosen for a preferred embodiment of the counter.
The interrupt generator counter is preferrably accessible via a PCI bus by the host. The interrupt registers which contain codes for the interrupt source are required to be zero upon putting the device to sleep. Thus, upon wake-up, the microprocessor will detect no interrupt code and will conclude that the interrupt corresponds to a clock wake-up and that transmission and reception of data is now possible.